Espressif Systems /ESP32-P4 /SOC_ETM /EVT_ST6_CLR

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Interpret as EVT_ST6_CLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR)PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR 0 (PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR)PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR 0 (PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR)PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR 0 (PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR)PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR 0 (PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR)PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR 0 (PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR)PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR 0 (PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR)PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR 0 (PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR)PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR 0 (PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR)PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR 0 (PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR)PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR 0 (PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR)PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR 0 (PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR)PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR 0 (PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR)PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR 0 (PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR)PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR 0 (PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR)PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR 0 (PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR)PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR 0 (PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR)PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR 0 (PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR)PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR 0 (PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR)PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR 0 (PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR)PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR 0 (PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR)PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR 0 (PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR)PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR 0 (PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR)PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR 0 (PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR)PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR 0 (PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR)PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR 0 (PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR)PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR 0 (PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR)PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR 0 (PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR)PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR 0 (PMU_EVT_SLEEP_WEEKUP_ST_CLR)PMU_EVT_SLEEP_WEEKUP_ST_CLR 0 (DMA2D_EVT_IN_DONE_CH0_ST_CLR)DMA2D_EVT_IN_DONE_CH0_ST_CLR 0 (DMA2D_EVT_IN_DONE_CH1_ST_CLR)DMA2D_EVT_IN_DONE_CH1_ST_CLR 0 (DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR)DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR

Description

Events trigger status clear register

Fields

PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR

Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\0: Invalid, No effect\1: Clear

PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR

Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\0: Invalid, No effect\1: Clear

PMU_EVT_SLEEP_WEEKUP_ST_CLR

Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\0: Invalid, No effect\1: Clear

DMA2D_EVT_IN_DONE_CH0_ST_CLR

Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status.\0: Invalid, No effect\1: Clear

DMA2D_EVT_IN_DONE_CH1_ST_CLR

Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status.\0: Invalid, No effect\1: Clear

DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR

Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status.\0: Invalid, No effect\1: Clear

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